1. Field of Invention
The present invention relates to integrated circuits. More particularly, the present invention relates to a digitally controlled tuner circuit for continuous-time filters.
2. Description of Related Art
To implement a continuous-time filter, various techniques and architecture have been developed. Widely used approaches employ transconductance-capacitor (gm-C) technique, active resistor-capacitor (active RC) type architecture, or MOSFET-capacitor (MOSFET-C) architecture.
When the process variation and temperature drift cause variations of active and passive devices, including the resistor and capacitor, the cutoff frequency of a continuous-time filter may drift and be unstable. For example, 3-dB bandwidth may have huge drift due to the drift of the cutoff frequency. Besides, variations of the resistance and/or capacitance also result in the variation of RC time constant. These facts described above all cause a continuous-time filter to be in an unstable condition.
FIG. 1 illustrates architecture of a traditional analog phase-locked loop (PLL) for tuning a continuous-time filter. The PLL in FIG. 1 consists of a phase/frequency detector (PFD) 100, a voltage-controlled oscillator (VCO) 110, a charge pump circuit 120, and a closed-loop filter 130. An input reference signal 102 is supplied to the PFD 100. The PFD 100 produces two outputs that indicate the frequency or phase difference between the reference signal 102 and the output signal of the VCO 110. The outputs of the PFD 100 are supplied to the charge pump circuit 120 and the closed-loop filter 130 generates a corresponding DC control voltage 140. The control voltage 140 is used to tune and control a continuous-time filter (not shown in FIG. 1). In addition, the control voltage 140 is also used to control the frequency of the output signal of the VCO 110. During the operation of the PLL in FIG. 1, PFD 100 and the charge pump circuit 120 function and adjust the control voltage 140, so that the frequency of the output signal of the VCO 110 tracks and approaches the frequency of the reference signal 102. When the frequencies of the two signals are close enough, the PFD 100 starts to perform phase lock.
However, the shortcomings of the above PLL include the following. When the control voltage 140 varies with process and temperature variations, the bandwidth of the continuous-time filter tuned by the control voltage 140 also varies and is unstable. Although the drift of bandwidth can be alleviated to a certain extent if the closed-loop filter 130 has a large RC time constant, the price for a large time constant is that the closed-loop filter 130 will occupy a huge hardware or require external components. Besides, the quality of the DC control voltage 140 is dependent on the phase noise and jitter performance of the PLL.